Most electronic equipment generates electromagnetic interference (EMI). EMI of one piece of equipment can affect the operation of other equipment in the vicinity of the first equipment. In the United States all electronic equipment must meet rules for electromagnetic emissions set forth by the Federal Communications Commission (FCC). These rules are designed to ensure that EMI from one piece of equipment does not affect other electronic equipment. The FCC rules specify how much energy a piece of electronic equipment may radiate at any particular frequency and at a particular distance.
Digital electronics and digital circuits typically require one or more clock signals, each with its own predetermined frequency. For example, in personal computers (PCs), the system clock signal can have a high frequency, such as 200 MHz. This clock signal is connected to multiple components so that the wire or trace on a circuit board can be relatively long. Since a long wire acts as an antenna, the clock signal can cause the PC to radiate or emit large amounts of energy at the clock frequency and its harmonics. These EMI emissions can make the task of complying with the FCC rules for EMI emissions very difficult if not impossible.
A well-known technique to reduce the peak EMI energy is to spread the spectrum of the clock. Phase-locked loop (PLL) circuits have been used to provide precise clock signals in a variety of applications in electronics.
There are many applications that require frequency synthesis (i.e., modulating the frequency of a signal (e.g., a carrier signal)). There are many ways to achieve spread spectrum, which is also know as dithering. One way to achieve dithering is to use a phase-locked loop (PLL). One prior art approach is illustrated in FIG. 1. FIG. 1 illustrates a prior art phase-locked loop (PLL) design 2. The phase-locked loop (PLL) design 2 includes a voltage-controlled oscillator (VCO) 4, a P-counter 6, a Q-counter 8, a phase detector 10, a charge pump 12, and loop filter 13.
The voltage controller oscillator (VCO) 4 generates a clock signal with a frequency that depends on its input voltage (i.e., the voltage at the V_ctrl node). The VCO includes an output that is coupled to the output node of the phase locked loop and generates an output clock signal (F_out). The input of the VCO 4 is also coupled to the loop filter 13 and the V_ctrl node. When the VCO input voltage changes, the frequency of the output clock signal changes in a linear fashion. For example, when the input voltage increases, the frequency of the output clock signal increases in a linear fashion. Similarly, when the input voltage decreases, the frequency of the output clock signal decreases in a linear fashion.
The P-counter 6 includes an input coupled to the output of the VCO 4. The P-counter has a first register for storing a first P value (e.g., P0) and a second register for storing a second P value (P1). The first P value (P0) and second P value (P1) represent two different integers that can be used to divide down the output frequency (F_out).
The P-counter 6 divides the frequency of the input signal by a predetermined number. For example, the P-counter 6 typically outputs a clock signal that has a feedback frequency (F_fb), which is an integer fraction of the frequency (F_out) of the clock signal generated by the VCO 4. The output (F_fb) of the P-counter 6 is coupled to an input of the phase detector 10.
The Q counter 8 includes an input for receiving an input frequency signal (F_in) and an output for generating a reference frequency (F_ref). The Q-counter 8 typically divides the input frequency (F_in) by a predetermined integer (Q) to generate a corresponding reference frequency (F_ref). For example, the reference frequency (F_ref) is an integer fraction of the input frequency (F_in).
The phase detector 10 includes a first input coupled to the output of the Q counter 8 for receiving the F_ref signal, a second input coupled to the output of the P counter 6 for receiving the F_fb signal, and an output for generating an up control signal and a down control signal. The charge pump 12 is coupled to the phase detector 10 for receiving the up and down control signals and for selectively charging (up) and discharging (down) the voltage control node (V_ctrl node) based on the up and down control signals.
The phase detector 10 compares the reference frequency (F_ref) with the feedback frequency (F_fb) provided by the P-counter 6. When the phase of the two input signals is not the same, the phase detector 10 controls the charge pump 12 to add or remove charge from the loop filter. A publication entitled, “Charge-Pump Phase-Lock Loops” Floyd M. Gardner IEEE Trans. Comm., vol. COM-28, pp 1849–1858, November 1980, further describes the interaction of the phase detector and the loop filter.
The adjustment of the input to the VCO 4 increases the frequency of the clock output of the VCO 4 (speeds up the signal) or decreases the frequency of the clock output of the VCO 4 (slows down the signal). By so doing, the PLL can provide a stable and steady clock output signal with a “locked” frequency.
For the PLL, the output frequency is related to the input frequency by the following expressions:                F_out=F_in*P/Q, where P and Q are integers that are loaded into the P-counter and Q-counter, respectively.        
As described earlier, in order to reduce EMI emissions, spread-spectrum PLLs are important to generate clock signals in digital designs, for example. In dithering or spread spectrum mode, the values loaded in the P-counter alternate or switch between two different values (e.g., P0 and P1). Alternating values of P cause the F_fb to alternate, which causes F_out to vary between a first output frequency and a second output frequency. The rate at which the output frequency varies with respect to time is referred to as the modulation frequency.
A spread-spectrum PLL has a frequency response with respect to time that resembles a triangle wave. Consequently, this approach is also called triangle wave dithering. There are different approaches to implement triangle wave dithering.
A first drawback of this scheme is that setting the output of the P-counter to one of two different frequency values may introduce instability into the loop dynamics of the PLL. For example, the jump between a first frequency and a second frequency can cause the PLL to come “out of lock.” A second drawback of this scheme is that this approach causes difficult timing problems, especially at higher frequencies. For example, when the output frequency of the VCO is 1 GHz or greater, it becomes a technical challenge for the P-counter to load in an alternate fashion P0 and P1 in a timely manner.
There are many circuits developed to attempt to solve the timing problems described earlier. Unfortunately, these circuits that are designed to overcome the timing issues often further disturb loop dynamics that may lead to instability in the PLL and “unlocking” of the frequency. Even if these circuits do not lead to instability of the PLL, they often degrade the performance of the PLL.
One approach is described in U.S. Pat. No. 5,610,955 that is directed to a PLL design that modulates the Q-counter with two values Q0 and Q1 to change the input of the VCO and provide dithering. Unfortunately, one disadvantage of this approach is that the design can introduce instability into the loop dynamics, thereby causing the loop to go out of lock. For example, instability can be introduced into the loop dynamics by changing the phase of reference frequency (F_ref).
An attempt to solve the timing issues related to the use of two frequency values in the p-counter involves complex analog circuits to implement special p-counter divider circuits. Unfortunately, one disadvantage of this approach is that it requires a high level of design skill of an analog design specialist, who may be difficult to locate. Furthermore, this approach typically realizes circuits, whose performance depends on the manufacturing process employed. Consequently, when a new manufacturer is selected to make the circuit, these circuits may require to be re-designed, thereby wasting resources.
Based on the foregoing, there remains a need for a circuit that provides dithering that overcomes the disadvantages set forth previously.